SRAM is a static RAM module. SRAM comes in dedicated bank sizes from 64 up to 1024 in 64 steps. SRAM data size can be either a byte or word. The WADDRESS bus defines the location of the data to be written. The RADDRESS bus defines the location of the data to be read back. The output data shows results on the RADDRESS decode. The SRAM data is written when the write pin is enabled.
There are three options for writing to the SRAM, either direct or counter.
- With a pin option, the user controls when the data is written.
- With register option, the REGISTERMAP generates a bit that controls a write sequence.
- With count option there is a built in address counter. The ‘reset ’will reset the address counter. The ‘clock’ input will control the write sequence. When clock goes high, the SRAM register that the counter is pointing to is written. On the next clock rising edge the address pointer is incremented. This sequence is repeated until the SRAM counter is full, at which point the ‘full_address’ flag is set.
- There is also an option for ‘built-in-self_test’. If BIST is selected a test sequence is run during test verification that verifies all bits in the SRAM. When BIST is initiated, a request for a 20MHz clock is sent. Once the request is acknowledged the sequencer writes/reads a defined pattern through the SRAM. When the sequencer is complete, a bist_done flag is set. If correct r/w data are passed, a bist_good flag is set.
The initial bist sequence code are
- ALL: 0x00, 0xFF
- OPPOSITE: 0x5A,0xA5
- PAIR: 0x69,0x96
- WATERFALL: 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
- LSB: 0xFF, 0xFE,0xFD,0xFB,0xF7
- MSB: 0xEF,0xDF,0xBF,0x7F,0x00